Autor: Scream (scream_at_w.pl)
Data: Sun 26 Nov 2000 - 09:49:53 MET
> a jestes _absolutnie_ pewien, ze ta pamiec jest nonvolatile ?
> bo jesli to po prostu mikrokod, tak jak w poprzednich procach,
> to nie jest to afaik wielki problem. zas jesli jest... coz,
> kolejny powod, dla ktorego pecetowy hw jest smieszny ;->
oto fragment z innej grupy dyskusyjnej:
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On Sun, 19 Nov 2000, AdamWozniak++ wrote:
> Fakt 1.
> Niektóre procesory (np. PIII) posiadają ROM z mikrokodem (jak się zaraz
> okaże nie jest on całkiem "read only").
Fakt... Czytaj nizej :)
> Fakt 2.
> Istnieje pewna możliwość (nie mam pojęcia jaka) zmiany zawartości tegoż
> ROM'u.
Fakt... :))
> Wniosek 1.
> Istnieje jakaś czysto software'owa możliwość modyfikacji zawartości
> ROM'u w niektórych procesorach Intel'a.
>
> Wniosek 2.
> Całkiem prawdopodobne może być to, że prędzej czy później może pojawić
> się wirus który zaatakuje sam procesor (powodując, że będzie on np.
> wolniej działał lub spowoduje, że działać po prostu przestanie).
To teraz ja pocytuje, tyle ze manual Intela :)
----------------------------------------------
8.10. P6 FAMILY MICROCODE UPDATE FEATURE
P6 family processors have the capability to correct specific errata
through the loading of an Intel-supplied data block. This data block is
referred to as a microcode update. This chapter describes the underlying
mechanisms the BIOS needs to provide in order to utilize this feature
during system initialization. It also describes a specification that
provides for incorporating future releases of the microcode update into
a
system BIOS.
Intel considers the combination of a particular silicon
revision and the microcode update as the equivalent stepping of the
processor. Intel does not validate processors without the microcode
update loaded. Intel completes a full-stepping level validation and
testing for new releases of microcode updates.
A microcode update is used to correct specific errata in the
processor.
The BIOS, which incorporates an update loader, is responsible for
loading
the appropriate update on all processors during system initialization
(refer to Figure 8-7). There are effectively two steps to this process.
The first is to incorporate the necessary microcode updates into the
BIOS,
the second is to actually load the appropriate microcode update into the
processor.
[cut]
8.10.2. Microcode Update Loader
This section describes the update loader used to load a microcode
update
into a P6 family processor. It also discusses the requirements placed
upon
the BIOS to ensure proper loading of an update.
The update loader contains the minimal instructions needed to load an
update. The specific instruction sequence that is required to load an
update is dependent upon the loader revision field contained within the
update header. The revision of the update loader is expected to change
very infrequently, potentially only when new processor models are
introduced.
The code below represents the update loader with a loader revision of
00000001h:
mov ecx,79h ; MSR to read in ECX
xor eax,eax ; clear EAX
xor ebx,ebx ; clear EBX
mov ax,cs ; Segment of microcode update
shl eax,4
mov bx,offset Update ; Offset of microcode update
add eax,ebx ; Linear Address of Update in EAX
add eax,48d ; Offset of the Update Data within the Update
xor edx,edx ; Zero in EDX
WRMSR ; microcode update trigger
8.10.2.1. UPDATE LOADING PROCEDURE
The simple loader previously described assumes that Update is the
address of a microcode update (header and data) embedded within the code
segment of the BIOS. It also assumes that the processor is operating in
real mode. The data may reside anywhere in memory that is accessible
by the processor within its current operating mode (real, protected).
Before the BIOS executes the microcode update trigger (WRMSR)
instruction the following must be true:
+ EAX contains the linear address of the start of the update data
+ EDX contains zero
+ ECX contains 79h
Other requirements to keep in mind are:
+ The microcode update must be loaded to the processor early on in the
POST, and always prior to the initialization of the P6 family
processors
L2 cache controller.
+ If the update is loaded while the processor is in real mode, then the
update data may not cross a segment boundary.
+ If the update is loaded while the processor is in real mode, then the
update data may not exceed a segment limit.
+ If paging is enabled, pages that are currently present must map the
update data.
+ The microcode update data does not require any particular byte or word
boundary alignment.
----------------------------------------------
i co ?
Jedyną możliwością, aby sprawdzić, czy rzeczywiście można zniszczyć procesor
przez zmianę mikrokodu, jest napisanie takiego programu i wypróbowanie go
:))) Kto się podejmie ? :)))
Ja niestety nie znam się na assemblerze :((
-- ..:: best.regards .::. kamil/scream/rydzynski ::.. || mobile +48-607-114-903 ..::.. scream(at)w.pl || Warszawska Gielda Komputerowa ,, http://wgk.waw.pl
To archiwum zostało wygenerowane przez hypermail 2.1.7 : Tue 18 May 2004 - 20:55:45 MET DST