Autor: Miroslav Goldberg (miroslav_at_usa.net)
Data: Sun 25 Jan 1998 - 21:49:09 MET
DRAM Read Burst
Set the timing for burst-mode reads from DRAM. The lower the timing numbers, the
faster the system addresses memory. Selecting timing numbers lower than the
installed DRAM is able to support can result in memory errors.
DRAM Write Burst
Set the timing for burst-mode writes from DRAM. The lower the timing numbers, the
faster the system addresses memory. Selecting timing numbers lower than the
installed DRAM is able to support can result in memory errors.
DRAM R/W Leadoff Timing
Select the combination of CPU clocks the DRAM on your board requires before each
read from or write to the memory. Changing the value from the setting determined by
the board designer for the installed DRAM may cause memory errors.
DRAM Fast Leadoff
Select Enabled to shorten the leadoff cycles and optimize performance.
Fast EDO Leadoff
Select Enabled only for EDO DRAMs in either a synchronous cache or a cacheless
system. It causes a 1-HCLK pull-in for all read leadoff latencies for EDO DRAMs
(i.e., page hits, page misses, and row misses). Select Disabled if any of the DRAM
rows are populated with FPM DRAMs.
Turbo Read Leadoff
Select Enabled to shorten the leadoff cycles and optimize performance in cacheless,
50-60 MHz, or one-bank EDO DRAM systems.
DRAM Speculative Leadoff
A read request from the CPU to the DRAM controller includes the memory address of
the desired data. When Enabled, Speculative Leadoff lets the DRAM controller pass
the read command to memory slightly before it has fully decoded the address, thus
speeding up the read process.
Fast EDO Path Select
When Enabled, a fast path is selected for CPU-to-DRAM read cycles for the leadoff,
providing the system contains EDO DRAMs. It causes a 1-HCLK pull-in for all read
leadoff latencies (i.e., page hits, page misses, and row misses).
Turn-Around Insertion
When Enabled, the chipset inserts one extra clock to the turn-around of back-to-back
DRAM cycles.
DRAM RAS# Precharge Time
The precharge time is the number of cycles it takes for the RAS to accumulate its
charge before DRAM refresh. If insufficient time is allowed, refresh may be
incomplete and the DRAM may fail to retain data.
Fast MA to RAS# Delay
The values in this field are set by the system board designer, depending on the DRAM
installed. Do not change the values in this field unless you change specifications
of the installed DRAM or the installed CPU.
MA Additional Wait State
Selecting Enabled inserts an additional wait state before the beginning of a memory
read. The setting of this parameter depends on the board design. Do not change from
the manufacturer's default unless you are getting memory addressing errors.
RAS# to CAS# Delay
This field lets you insert a timing delay between the CAS and RAS strobe signals,
used when DRAM is written to, read from, or refreshed. Disabled gives faster
performance; and Enabled gives more stable performance.
DRAM Page Idle Timer
Select the amount of time in HCLKs that the DRAM controller waits to close a DRAM
page after the CPU becomes idle.
DRAM Enhanced Paging
When Enabled, the chipset keeps the page open until a page/row miss. When Disabled,
the chipset uses additional information to keep the DRAM page open when the host may
be "right back."
SDRAM Speculative Read
The chipset can "speculate" on a DRAM read address, thus reducing read latencies.
The CPU issues a read request containing the data memory address. The DRAM
controller receives the request. When this field is Enabled, the controller issues
the read command slightly before it has finished decoding the data address.
SDRAM (CAS Lat/RAS-to-CAS)
You can select a combination of CAS latency and RAS-to-CAS delay in HCLKs of 2/2 or
3/3. The system board designer should set the values in this field, depending on the
DRAM installed. Do not change the values in this field unless you change specificat
ions of the installed DRAM or the installed CPU.
Refresh RAS# Assertion
Select the number of clock ticks RAS# is asserted for refresh cycles.
DRAM Refresh Queue
Enabled permits queuing up to four DRAM refresh requests, so DRAM can refresh at
optimal times. Disabled makes all refreshes priority requests. Installed DRAM must
support this feature; most do.
DRAM RAS Only Refresh
An alternate to CAS-before-RAS refresh. Leave Disabled unless your DRAM requires
this older method of refresh generation.
DRAM Refresh Rate
Select the period required to refresh the DRAMs, according to DRAM specifications.
Fast DRAM Refresh
The cache DRAM controller offers two refresh modes, Normal and Hidden. In both
modes, CAS takes place before RAS but the Normal mode requires a CPU cycle for each.
On the other hand, a cycle is eliminated by "hiding" the CAS refresh in Hidden mode.
Not only is the Hidden mode faster and more efficient, but it also allows the CPU to
maintain the status of the cache even if the system goes into a power management
"suspend" mode.
Read-Around-Write
DRAM optimization feature: If a memory read is addressed to a location whose latest
write is being held in a buffer before being written to memory, the read is
satisfied through the buffer contents, and the read is not sent the DRAM.
PCI Burst Write Combine
When this option is Enabled, the chipset assembles long PCI bursts from the data
held in these buffers.
PCI-To-DRAM Pipeline
DRAM optimization feature: If Enabled, full PCI-to-DRAM write pipelining is enabled.
Buffers in the chipset store data written from the PCI bus to memory. When Disabled,
PCI writes to DRAM are limited to a single transfer per write cycle.
CPU-To-PCI Write Post
When this field is Enabled, writes from the CPU to the PCI bus are buffered, to
compensate for the speed differences between the CPU and the PCI bus. When Disabled,
the writes are not buffered and the CPU must wait until the write is complete before
st arting another write cycle.
CPU-To-PCI IDE Posting
Select Enabled to post write cycles from the CPU to the PCI IDE interface. IDE
accesses are posted in the CPU to PCI buffers, for cycle optimization.
Peer Concurrency
Peer concurrency means that more than one PCI device can be active at a time.
Passive Release
When Enabled, CPU to PCI bus accesses are allowed during passive release. Otherwise,
the arbiter only accepts another PCI master access to local DRAM.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
Chipset Special Features
When disabled, the chipset behaves as if it were the earlier Intel 82430FX chipset.
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Mirek
To archiwum zostało wygenerowane przez hypermail 2.1.7 : Tue 18 May 2004 - 16:57:35 MET DST